Mitigating Obsolescence Risk Using Reconfigurable Logic Devices

This proposal uses Field Programmable Gate Array (FPGA) and System-on-a-Chip (SoC) to mitigate obsolescence issues in deployed processing systems. By abstracting input/output communications protocols from the processing system through use of programmable logic devices (PLDs), component upgrades and replacements can be performed that require simple firmware updates rather than hardware re-qualification. Further incorporation of cryptographic algorithms provides flexibility for future upgrades and/or interfaces with new components. This enables a reconfigurable real-time processing architecture that mitigates obsolescence risks. This effort involves establishing a design and subsequent implementation of the above concepts. Metrics are defined to evaluate the capabilities of this implementation.