High Performance Digital Cancellers

The Navy is seeking to develop and innovate adaptive and deterministic steering algorithms and key elements for nulling-aware routing for application on tactical data links to improve communication range, interconnectivity, and anti-jamming resistance. The algorithms must process at least two digitized antenna inputs in a Field Programmable Gated Array (FPGA) to provide 30-60 dB communications resilience improvement in a contested environment. Algorithms should also accept and provide Direction of Arrival (DOA) parameters that allow higher protocol layers to perform cooperative nulling, trades between nulling adversarial and friendly nodes to preserve interconnectivity and data dissemination capability. Bedford Signals canceller implementations include coefficient generation using a General Purpose Processor (GPP), or ultra-fast converging FPGA based systolic coefficient generation. Our architectures include low latency ultra-fast converging Space Time Adaptive Processing (STAP) and resource efficient Space Frequency Adaptive Processing (SFAP). These solutions include techniques to preserve Signal of Interest (SOI) waveforms during interference cancellation. Enhancements support array calibration and emitter DOA determination for integration with wireless and interference aware higher protocol layers.