SBIR/STTR Research Award

Computational Pixel Imager (CPI) Readout Integrated Circuits for Next Generation High Performance and Low SWaP Sensors

Award identifier ef166a7c85126173ebc7b62e391c429c9b765bacabfbd277911572511b11a098Awarding agency National Aeronautics and Space Administration

Award amount

$123,235

Program and phase

SBIR · Phase I

Award year

2019

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
Copious Imaging LLC
Proposal award date
2019-08-19
Contract end date
2020-02-18
UEI
KE5NNF1FM1J3
Solicitation number
SBIR_19_P1
Topic code
S1

Research abstract

We propose to leverage on-going CPI work to enable a low-cost and low-risk program approach that can be executed as a Phase I SBIR program.nbsp; The scope of this phase I effort is limited to studying the feasibility of some fundamental parameters of a design targeting HOT MWIR and high data-rate FTIR applications.nbsp;nbsp; The following technical aspects of a NASA CPI design will be explored:nbsp;Model the basic CPI ROIC specifications needed to support NASA earth science and inter-planetary missions.nbsp; For HOT IR missions, survey thermo-electric cooler availability and performance as well as the needed LSB size to support shot-noise limited performance.nbsp; This will help form the power budget for the device.nbsp; For FTIR missions, explore availability of ldquo;2-colorrdquo; detector arrays and Avalanche Photodiodes (APD) for meeting stated requirements.nbsp; Evaluate the potential for meeting requirements with or without APD detector arrays.nbsp;Methods for reducing the quantization noise floor, which defines the performance associated with the least significant bit (LSB) of the digitized data. Past designs typically achieve approximately 2000e- as the minimum LSB size.nbsp; Experimental designs have achieved as low as 1e- LSB size, but with noise and linearity issues present.nbsp; The goal of this effort will be to explore new designs and feasibility to achieve between 30 ndash; 500e- LSB size with a low power and high performance front-end design.nbsp;nbsp;nbsp;Design trades to determine what counter bit depth can be accomplished as a function of pixel size to achieve global shuttering, read-while integrate, orthogonal transfer, and ldquo;2-colorrdquo; detector operation.nbsp; Several process nodes will be considered at Fabs found both on- and off-shore.nbsp; ITAR or EAR restrictions may limit the choice of Fabs in the long run, however this limitation will not be a consideration in this study.nbsp;

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

4 SBIR/STTR records share this UEI (2019–2020). Reported award amounts total $1,970,580. Reported amounts are not federal obligations.

Phases: Phase I, Phase II – Direct to Phase II, Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration

Agency intelligence

National Aeronautics and Space Administration

Back to SBIR/STTR Research Awards

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