Extreme Environment System Integration Techniques for Venus In-Situ Processing

NASA has demonstrated a resolve to land instruments on the corrosive, high-pressure (~100 bar), high-temperature (470deg;C) surface of Venus. NASA Glenn Research Centerrsquo;s JFET-R technology is the only one that has shown 1000rsquo;s of hours operation under Venus surface conditions. The limitation of this process is that the current integrated circuit die and feature sizes make it impractical for large complex designs. Ozark IC has developed high-temperature packaging technology capable of integrating several JFET-R die onto a single layer substrate. Complex Venus-surface ICs, such as a microprocessor, can be created by marrying these two technologies.The objective for this proposal is a multi-chip packaging technology that hosts several JFET-R die to effectively create complex electronic functions for Venus surface conditions.The project will utilize additive and subtractive manufacturing techniques to create high-temperature single-connector terminals, high temperature/high density multiple conductor connectors, and single or multiple level high-temperature substrates. This, in combination with NASArsquo;s JFET-R technology will create a design technology which will be used to develop a multi-chip high-temperature microprocessor. These advancements in terminal and board manufacturing design should enable denser chip designs. Several prototype connectors will be designed, manufactured, and tested. Once a reliable connector and board system has been identified, an integrated module will be tested at 470deg;C.Questions to be answered during the Phase 1 are:Is it possible to create a high-temperature connector reliable enough for Venus surface conditions?What package density can be achieved?What performance can be expected?