SBIR/STTR Research Award
Secure Processor Features for the Enforcement of Separation Kernels
Award amount
$99,985Program and phase
SBIR · Phase IAward year
2019Award details
- Awarding agency
- Department of Defense
- Branch
- Army
- Recipient company
- IDAHO SCIENTIFIC LLC
- Proposal award date
- 2019-02-06
- Contract end date
- 2020-03-15
- UEI
- DNE7MBEM1C45
- Solicitation number
- 18.3
- Topic code
- A18-133
Research abstract
Idaho Scientific presents a Risc-V based secure processor architecture that provides unique security properties complimentary to the seL4 microkernel. The work conducted under this Phase I SBIR effort will further the discipline of computer security by mitigating memory corruption vulnerabilities, enforcing strong processes separation, covering seL4's formal verification assumptions, and provide a path to close physical anti-tamper vulnerabilities.
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- Helios: Dual-Purpose Secure Processor
- Secure Assured Filed Transfer (SAFe-T) Drive
- Secure Assured File Transfer Drive
- Embedded Class Secure Processor
- Secure Protocol Unalterable Data (SPUD) Phase II
Awards with the same topic code
Verified by an exact topic code match. This is not a text-similarity match.
- seL4 on RISC-V for Secure U.S. Army Applications
- High Assurance Systems via the Open Source seL4 Microkernel and Open RISC-V Processor
Research funding history
8 SBIR/STTR records share this UEI (2016–2024). Reported award amounts total $45,691,423. Reported amounts are not federal obligations.
Phases: Phase I, Phase II, Phase II – Direct to Phase II
Agencies: Department of Defense, Department of Energy