Photonic Integrated Circuit Reliability Modeling Methodology to Enable Standardization

The DoD S&T community’s understanding of photonic integrated circuit (PIC) and related Planar Lightguide Circuit (PLC) reliability has gaps preventing full PIC deployment to defense avionics. Validation of PIC reliability is critical to enabling rapid transition to DoD programs. IFOS is leveraging its proven expertise in PIC-based systems to develop PIC reliability prediction models. We will leverage knowledge from established semiconductor Integrated Circuit (IC) and renewable energy industries including automotive and solar, infuse the relevant subjects with emerging PIC reliability data, and augment remaining gaps with Highly Accelerated Life Test (HALT) methodology. In Phase I, IFOS will establish approaches to model intra-chip PIC reliability and develop experimental test plans based on various degradation phenomena and failure modes. In Phase II, IFOS will populate and validate the reliability prediction models with PIC environmental, electro-optical, and mechanical testing. The reliability models will be implemented in a software toolkit for independent verification. The associated methodology will be subjected to reliability community debate to enable standardization and industry adoption. To accomplish the stated objectives and significantly mitigate program risks, IFOS has assembled a world-class multidisciplinary team of microelectronic and photonic chip-level expertise, together with reliability testing and software toolkit development specialties.