Building Die Extracted/Repackaged (DER)-Optical Hybrid Integrated Circuits (ICs) to Replace Passive Devices and Obsolete Packaged ICs in a Line Replaceable Unit (LRU) to Enhance Performance, Reliabili

Photonic integrated circuit (PIC) development and silicon integration can benefit from die extraction and re-packaging (DER) by making PIC devices more available in bare die form for faster prototyping of multi-chip modules and assemblies.Global Circuit Innovations has developed a technology roadmap blending DER, additive manufacturing, and vertical-cavity surface-emitting laser photonic devices, or VCSELs. A VCSEL is a semiconductor-based laser diode that emits a highly efficient optical beam vertically from its top surface.Active lens alignment/collimation of the emitting light for a VCSEL is time-consuming and relatively expensive today.GCI proposes creating a variety of lens sizes, shapes, and pitches with additive manufacturing to execute a design of experiments (DOE) to develop a more efficient and cost-effective passive VCSEL collimation process.The Phase I is designed to assess the manufacturability of a wafer-level collimating process using a two dimensional intensity map alignment process with a fish eye to monitor the collimated intensity. We anticipate initially using an 850 nm wavelength option, while attempting to gang a VCSEL array to increase power and intensity output. The Phase II will concentrate on passive lens development and integration using a conformal coating that is disrupted and self-aligned by the emitting VCSEL emission.