12-bit 32 Channel 500MSps Low Latency ADC

Particle accelerators need precise, real-time control of the particle beams used to create the conditions required for Nuclear Physics (NP) experiments. The digital feedback of these control systems requires low latency ADCs with high linearity and dynamic range. High performance multichannel digitizers dissipate excessive heat. Therefore, low power dissipation is another critical requirement for ADCs. Currently available 12-bit 500MSps ADCs include only 2 channels and require 12 clock cycles per conversion. Pacific Microchip Corp. proposes to develop a 12-bit 32 channel (operating in parallel) 500MSps low latency, low power ADC ASIC. The ADC will employ a novel two-step conversion architecture based on a merged sample & hold (S/H) circuit, a residue C-DAC and a shared 6-bit flash core ADC. The core ADC will provide coarse and fine digitization, one after another, by using two cycles. The proposed 2- step ADC will feature a flash-like performance using just a fraction of the on-chip area and power consumption compared to a regular flash ADC.Within Phase I, the ADC’s architecture was developed and modeled, the critical circuits were designed and the proof of feasibility at architectural and circuit level was provided based on simulations. Phase II will result in the fabricated and tested ADC ASIC’s prototype ready for commercialization in Phase III. Commercial applications and other benefits: Due to the increasing role of digital signal processing in the state of the art electronic systems, an ADC becomes a generic building block employed to perform direct digitization and multichannel signal processing for a great number of applications including sensor systems, control loops and RF receivers. Thus, the multichannel low power, high sampling rate 12-bit ADC will be demanded for a large number of tasks. Radiation hardness will expand the proposed ADC ASIC’s applicability to other DOE and NASA science programs and to the systems under development by the industry. To ensure the highest outcome of the developed technology, we plan to license the ASIC as an IP block to other interested parties for integration with other blocks (both analog and digital) for a system-on-a-chip (SoC) solution. According to the latest market study released by Technavio, the global data converter market is expected to reach $4.24 billion by 2020, growing at a CAGR of almost 6%. This projection confirms the great commercial potential for the proposed ADC.