AN ULTRA-FAST SAMPLING ADC ASIC INTERFACING WITH FPGAS

Pacific Microchip Corp. proposes to develop an ultra-high (56GHz) sampling rate 8-bit ADC ASIC with a JESD204C interface convenient for data transfer to FPGAs. The proposed ADC ASIC is primarily targeted for spectrometer applications, especially those that require using FPGAs rather than ASICs for digital signal processing. These applications include unique signal processing functions required in instruments used for microwave remote sensing of Earth from space or for applications that require hardware-based evaluation before these solutions can be transferred to ASICs. The proposed solution will leverage a previously developed and silicon-proven 8-bit 56GS/s ADC IP block (DARPA award D17PC00116). Within the proposed project we will implement the JESD204C standard compliant output data interface which includes the 64B/66B encoding for bandwidth efficient data transmission at 32x14.4Gb/s, which is convenient for data interfacing with off-the-shelf FPGAs. The ASIC will also include new calibration algorithms required to achieve the 6-bit ENOB and 28GHz bandwidth. Within the Phase I project, we will prove the feasibility of the ADC ASIC implementation and achieving the 28GHz bandwidth, 8-bit resolution and 6-bit ENOB at 56GS/s rate. The project’s Phase II will produce a fieldable ASIC for the NASA instrumentation.