AN ULTRA-FAST SAMPLING ADC ASIC INTERFACING WITH FPGAS

Pacific Microchip Corp. proposes to develop an ultra-fast (56GHz) 8-bit ADC ASIC with an enhanced data rate JESD204B interface, designed for efficient and convenient data transfer to FPGAs. This ADC ASIC is primarily intended for spectrometer applications, particularly those requiring the use of FPGAs for digital signal processing instead of ASICs. Such applications include specialized signal processing functions needed in instruments used for microwave remote sensing of Earth from space, or in scenarios where hardware-based evaluation is necessary before transitioning spectrometer solutions to ASICs. The proposed ADC ASIC builds upon a previously developed and silicon-proven 8-bit 56 GS/s ADC IP block, developed under a DARPA award (D17PC00116). This ASIC will incorporate an enhanced rate JESD204B standard-compliant output data interface for bandwidth-efficient data transmission over 20 lanes of 28 Gb/s, ensuring seamless data interfacing with off-the-shelf FPGAs. The ASIC will also include a CPU running new ADC calibration algorithms to achieve a 6-bit Effective Number of Bits (ENOB) and 28 GHz bandwidth. In Phase I, we demonstrated the feasibility of the ADC ASIC achieving a 28 GHz bandwidth, 8-bit resolution, and 6-bit ENOB value at a 56 GS/s sampling rate. Phase II will result in the production of a deployable ASIC for NASA instrumentation.