Rad-Hard Embedded Processing SIP

VORAGO Technologies has created a product design and MIL-PRF-38534 qualification plan for a radiation-hardened miniaturized System-In-Package (SIP) that comprises an ARM® Cortex®-M0 microcontroller (VORAGO VA10820), a 16-channel 14-bit analog-to-digital converter (Cobham RHD5950) and a 2Mbit FRAM (Cypress CYRS15B102). All the design work and planning has been put in place to produce working packaged SIP devices and qualify them in phase II.Each of the three rad-hard die will be mounted on substrate within a hermetic 68-pin ceramic package. Individual signals from each device are routed via the substrate within the chip, which also includes decoupling capacitors and pull-up resistors in the SIP. This optimizes the number of useful pins that are available to the system designer.The SIP design optimizes the size, user simplicity and reliability of the solution. Using this SIP solution rather than three discretely packaged parts means that the area of the functionality can be reduced by approximately a factor of five and the number of pin interconnections on a PCB can be reduced by a factor of more than three.In phase II, we propose to build 85units of the device and qualify it. In addition, we will build evaluation boards and a software board support package so that the device can be easily evaluated and used for development work by NASA engineers. Our objective is to get as many units / evaluation boards onto NASA engineers desks as possible.We have discussed this device with NASA engineers from GSFC, Ames, JPL, JSC and MSFC and have received very positive feedback that the SIP device would be useful to them and would help simplify and miniaturize their electronics designs. Comments from NASA engineers have been included in the Phase II Technical Proposal.