SBIR/STTR Research Award

Radiation-Hardened I/O Expansion Chip

Award identifier 19a9b63e729b4e81faea90a0bea7f12eeb7a274b1544ef38db5ceade131e0156Awarding agency National Aeronautics and Space Administration

Award amount

$747,761

Program and phase

SBIR · Phase II

Award year

2019

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
Silicon Space Technology Corporation
Proposal award date
2019-08-11
Contract end date
2020-07-10
UEI
H77JUZDAR365
Solicitation number
SBIR_18_P2
Topic code
S3

Research abstract

VORAGO Technologies has produced an IC definition and architecture for a rad-hard I/O Expansion chip that is capable of interfacing to next generation spaceflight processor devices including the High-Performance Spaceflight Computing (HPSC) chiplet.nbsp;We have gathered the best available knowledge of HPSC use-cases to conceptualize and articulate the requirements for an I/O Expansion Chip, creating an architecture for an optimized and robust IC that can be implemented to meet the requirements of next generation NASA space electronics systems.nbsp;nbsp;In addition to providing a perfect companion IC to the HPSC in next generation systems architectures, the I/O Expansion Chip can facilitate the use of the HPSC with legacy systems (such as those that include MIL-STD-1553 communications). Support of legacy systems is a practical requirement for the next decade. The I/O Expansion Chip will allow the HPSC to interface with legacy systems as well as next generation systems. We most recently added USB 3.0 to the definition to support camera interfaces that are being considered / selected for Orion and SPLICE programs at NASA Johnson Space Center.nbsp;VORAGO Technologies would like to commercialize the I/O Expansion Chip product and target sales to NASA and non-NASA commercial aerospace customers. Making the product commercially successful outside of NASA applications will increase sales volume and establish a more robust supply chain for the product.nbsp;In phase II, we propose to create a detailed IC specification, acquire the main IP blocks and create a hardware prototype system of the I/O Chip using the Synopsys HAPS80 prototyping system. This approach is consistent with that taken for the HPSC chiplet development process.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

33 SBIR/STTR records share this UEI (2005–2020). Reported award amounts total $18,593,887. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration

Agency intelligence

National Aeronautics and Space Administration

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