GR-TDM : A Framework for Design Space Exploration of Hardware Trojan Detection and Mitigation Tradeoffs

As integrated circuit dimensions shrink and U.S. fabrication facilities age, U.S. ASIC developers are increasingly turning to overseas foundries for the latest process nodes in device fabrication.This migration is especially impactful for DoD designers as critical military technology needs to be trusted and offshore fabrication has the potential to expose chips to malice during manufacture.Sensitizing designs to malicious insertions or providing additional functionality that improves the probability of untrusted operation detection at run-time can offset concerns regarding untrusted fabs.Pairing this approach with a trusted security monitor can enable a system to fight through previously unknown attacks by detecting faulty logic and preventing malice trigger operations or reconfiguring around them in real time.Our approach to the challenge of improving design tool support for Hardware Trojan Detection and Mitigation is to investigate a set of detection/prevention methods, tie these methods into techniques for calculating operational confidence gains, and integrate both the method insertion and tradeoff calculation into commercial EDA tools.The result will be a solution that enables design-time feedback regarding the trade-offs between performance, power, area, and increased confidence in device operation.This capability will benefit both DoD and commercial ASIC developers concerned with ensuring operational confidence.