Digital Erasure of Sensitive FPGA Systems

Increasing system complexities and a constant drive to reduce the size, weight, and power (SWaP) of deployable electronic systems has forced a reliance on Application Specific Integrated Circuits (ASICs).Ā ASICs can fill the complexity and SWaP needs but are expensive and time consuming to develop and deploy. These deployed electronic systems invariably contain sensitive information in the form of Intellectual Property (IP), configuration information, and transient operational data which may be Critical Program Information (CPI).Ā If those electronic systems fall outside the control of their authorized users, they can potentially be exploited to recover that information. Field Programmable Gate Arrays (FPGAs) provide an alternative with reconfigurable logic that is capable of hosting logic designs on general-purpose hardware to support rapid development and deployment of electronic systems.Ā FPGAs also provide a security advantage in the protection of sensitive information through their ability to be erased or zeroized when necessary. This program will continue development of a previously defined FPGA zeroization framework and tools to enable designers of FPGA-based electronic systems to confidently and efficiently integrate zeroization capabilities into their designs.