Enabling Large Format Deep Pixel Detectors Through 3D Quilt Packaging
Award amount
$149,976Program and phase
SBIR · Phase IAward year
2017Award details
- Awarding agency
- Department of Energy
- Branch
- Not reported
- Recipient company
- INDIANA INTEGRATED CIRCUITS LLC
- Proposal award date
- 2017-06-12
- Contract end date
- 2018-06-11
- UEI
- W1FUVNENSJN4
- Solicitation number
- DE-FOA-0001619
- Topic code
- 27g
Research abstract
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- PCB "Boardlets" for Modular, Scalable High-Performance Printed Circuit Assemblies"
- Cryogenic Adiabatic CMOS for Ultra-Low Power Circuits
- Adiabatic Circuits for Ultra-Low Energy Consumption
- Adiabatic Circuits for Ultra-Low Energy Consumption
- Heterogeneous Chip Integration for GHz Systems
Research funding history
7 SBIR/STTR records share this UEI (2013–2021). Reported award amounts total $1,587,206. Reported amounts are not federal obligations.
Phases: Phase I, Phase II
Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Energy