Adiabatic Circuits for Ultra-Low Energy Consumption

Indiana Integrated Circuits, LLC (IIC) and the University of Notre Dame, proposes to design, fabrication, and test/verification of an adiabatic reversible-logic microprocessor, building upon a very productive Phase I. The Phase I effort saw the successful design and verification of a 16-bit MIPS microprocessor using adiabatic logic in 90 nm CMOS. Simulations performed as part of the completed Phase I microprocessor design showed a 90% reduction in average power consumption compared with the conventional CMOS in the same 16-bit configuration, demonstrating the viability of adiabatic circuits as an ultra-low power alternative to CMOS. In Phase II the Phase I microprocessor design will be updated and optimized for compatibility with foundry design rules before taping-out for fabrication. The end result of the proposed Phase II effort is the test and validation of the physical implementation of the Phase I design. IIC is pursuing funding for Phase II enhancement options in addition to the base Phase II effort. These efforts are being sought based on interest by IIC’s commercial and DoD partners in either further developing the technology developed in Phase I for commercialization, or applying the technology to a specific end-use application.