SBIR/STTR Research Award
PCB "Boardlets" for Modular, Scalable High-Performance Printed Circuit Assemblies"
Award amount
$117,084Program and phase
SBIR · Phase IAward year
2021Award details
- Awarding agency
- National Aeronautics and Space Administration
- Branch
- Not reported
- Recipient company
- INDIANA INTEGRATED CIRCUITS LLC
- Proposal award date
- 2021-05-12
- Contract end date
- 2021-11-19
- UEI
- W1FUVNENSJN4
- Solicitation number
- SBIR_21_P1
- Topic code
- S3
Research abstract
The team of Indiana Integrated Circuits, LLC (IIC), and Calumet Electronics Corporation (CEC) propose the development and demonstration of an innovative approach for modularized, highly-scalable, high-performance printed circuit board (PCB) assemblies. By extending the chip-to-chip edge-interconnect technology known as ldquo;Quilt Packagingrdquo; from microchips to PCBs, multiple ldquo;boardletsrdquo; can be assembled into a mechanically robust PCB system comprised of disparate process technologies and substrate materials. Such an approach can be applied to optimize PCB systems for yield, cost, security, manufacturability, and highly customizable rapid manufacturing for a wide variety of NASA, defense, and commercial applications. nbsp;Quilt Packagingreg; (QP), is implemented using solid metal interconnection which protrude from the vertical side of a chip, allowing for virtually seamless edge-to-edge connection which is extremely low-loss and extremely wide bandwidth. Preliminary work by IIC has shown potential for similar edge-to-edge implementation between PCBs, eliminating or dramatically reducing the need for typical sockets, wiring and cabling while simultaneously improving electrical performance
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- Cryogenic Adiabatic CMOS for Ultra-Low Power Circuits
- Adiabatic Circuits for Ultra-Low Energy Consumption
- Adiabatic Circuits for Ultra-Low Energy Consumption
- Enabling Large Format Deep Pixel Detectors Through 3D Quilt Packaging
- Heterogeneous Chip Integration for GHz Systems