SBIR/STTR Research Award

Radiation Hardened High Speed Integrated Circuits Double Data Rate I/O for Extreme Operating Environments

Award identifier 45a1dbb2a19a252896cb5f120d62b056c074942ac93d1490cfb1a9d878e386f2Awarding agency National Aeronautics and Space Administration

Award amount

$124,954

Program and phase

SBIR · Phase I

Award year

2017

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
MICROELECTRONICS RESEARCH DEVELOPMENT CORPORATION
Proposal award date
2017-06-09
Contract end date
2017-12-08
UEI
M2WCCD39B593
Solicitation number
Not reported
Topic code
Z6.01

Research abstract

Manned and robotic space missions require high-performance electronic control systems capable of operating for extended periods in harsh environments that are subject to radiation, extreme temperatures, vibration and shock. Semiconductor technologies capable of meeting these demanding requirements tend to have limited capabilities, are expensive, and are not easily configured for specific mission requirements. Leading-edge applications will benefit from the ability to implement high speed interconnect protocols between host processors and system slaves, such as sensors, actuators, power managers, imagers and transceivers. The development of a Radiation Hardened Double Data Rate (DDR) embedded macro is proposed for insertion into digital integrated circuits (ICs) suitable for scalable single and multi-core processors, special purpose logic functions and scalable memory blocks on a space-qualified, radiation hardened integrated circuit digital fabric. A NASA-funded Structured ASIC architecture is under development at Micro-RDC, capable of meeting space-grade requirements while creating a cost-effective, quick-turn development environment. The SASIC fabric will implement known Radiation-Hardened-By-Design (RHBD) techniques on an advanced 32nm Silicon on Insulator (SOI) CMOS process, supporting high-density, high-speed low-power implementations. A unique Master Tile architecture with through-seal-ring connections allows the designer to define dedicated logic functions, scalable memory blocks and user-defined I/Os; all on a single, scalable integrated circuit. The 32nm SOI CMOS process technology platform incorporates RHBD building-blocks (e.g. flip-flops, gates, distributed memory, block memory, I/O) required for the systems designer to implement functional blocks for application-specific requirements. During this project, key blocks for a DDR3 macro will be specified and evaluated for optimum inclusion into the Micro-RDC SASIC.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

45 SBIR/STTR records share this UEI (2006–2019). Reported award amounts total $31,438,573. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration

Agency intelligence

National Aeronautics and Space Administration

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