20GSps 6-bit Low-Power Rad-Tolerant ADC

The proposed project aims to develop a 20GSps 6-bit ADC required for microwave radiometers being developed for space and airborne earth sensing applications and radio telescopes. Aiming to improve performance and to reduce the size of the electronics, high resolution, high-sampling rate, power efficiency and low spur energy are required for ADCs employed for direct digitization. The proposed 20GS/s 6-bit time-interleaved successive approximation (SAR) ADC is intended to achieve >5 ENOB and 20GHz input bandwidth. A number of innovations will be introduced to the ADC in order to combine low power consumption with high signal to noise and distortion (SINAD), and spurious free dynamic range (SFDR). The proposed ADC will employ a novel timing calibration and interleave randomizing techniques which permit minimizing the peak energy of the spurs and increasing linearity. The proposed ADC chip will include a frequency synthesizer and a standard compliant configurable JESD204B interface for data exchange with an FPGA. The ADC will be implemented using a deep submicron CMOS technology. The project's Phase I confirmed the feasibility of implementing the proposed ADC. Phase II will include finishing design, fabrication, testing and delivering the ADC prototypes which will be ready for commercialization in Phase III.