Low-Latency Embedded Vision Processor (LLEVS)

ABSTRACT: Digital binocular helmet-mounted display (HMD) systems are now available that allow high resolution wide field-of-view (WFOV) digital imagery to be displayed on high resolution microdisplays. These digital HMD systems require a low-latency embedded vision processor (LLEVS) capable of implementing the necessary image processing algorithms. An SA Photonics LLEVS will be implemented on next generation field-programmable gate array (FPGA) device for high performance as well as size, weight, and power (SWaP) savings. A next generation memory architecture will be used to achieve higher bandwidth at a much lower energy per bit. The LLEVS primary emphasis is low-latency, low power implementation of optical distortion correction, image registration, image fusion, and head tracking with high performance next generation camera and display interfaces. Next generation FPGA devices will operate at low enough power while providing enough processing capability for high frame rate throughput with sub-frame latency from sensors to microdisplays. Next generation data links will be utilized that can be used for sensor and display uplink/downlink and can also provide power.; BENEFIT: The innovative LLEVS that SA Photonics has developed has the following advantages over existing embedded video processor platforms: Implementation on next generation FPGAs for higher performance and lower power Next generation memory architecture for high bandwidth performance Low-latency warp correction, image fusion, and head tracking algorithms Multiple inputs and outputs for high bandwidth sensor and display transfer Vision and data link to platform Additional in-system functionality possible with application processor