Low-Latency Embedded Vision Processor (LLEVS)

High-performance low-latency image processing is needed in next-generation DoD vision systems. In LLEVS Phase II, we bring low-latency digital imaging and future fusion applications to the warfighter, in a scalable small-SWaP product footprint leveraging COTS technology.We have a very detailed LLEVS FPGA design resulting from our Phase I efforts. We understand the entire critical path of the design. We have performed preliminary LLEVS design work down to filter coefficients and schematics of the LLEVS processor. We have bounded Phase II power consumption estimates, which we will optimize and reduce. Finally, we have a risk-mitigating spiral development plan for Phase II. All of these factors combine to give high confidence in a successful Phase II LLEVS prototyping demonstration outcome.At the end of Phase II we will have both a low and high risk solution for LLEVS. We will have working hardware and software, and live binocular video demonstrations of extremely low latency video with high-order image processing, using actual commercial cameras and displays, and potentially EBAPS and eMagin sensors and microdisplays.Through our flexible strategy of IP licensing, SoM modules for rapid third-party incorporation of LLEVS, and dedicated LLEVS products, we see great things coming of this research effort.