SBIR/STTR Research Award

Low-Latency Embedded Vision Processor (LLEVS)

Award identifier d2d8c7136e3fca0a365502347091af073b27e9584b18f0fee3e5aaefde53d856Awarding agency Department of Defense · Air Force

Award amount

$149,999

Program and phase

STTR · Phase I

Award year

2015

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
Nanowatt Design, Inc
Proposal award date
2015-08-03
Contract end date
2016-04-29
UEI
JN6DTHPNBSK1
Solicitation number
2015.1
Topic code
AF15-AT13

Research abstract

ABSTRACT: The goal of head-worn display systems is to increase situation awareness and reduce operator workload. The urgent need is for higher image resolution and lower system latency, while meeting constraints on head-borne weight and power. Current processor solutions cannot meet increased requirements. The challenge is that power consumption is proportional to the amount of data being handled, which increases along with higher resolution and faster frame rates. This Small Business Technology Transfer Phase I project is to develop detailed plans for a low-latency embedded processor having fundamentally reduced energy per operation, enabling implementation of the image processing algorithms required for a digital helmet-mounted display for dismounted soldiers. Two plans for designing a vision-processor helmet system in Phase II and fabricating the processor in Phase III will be developed during the Phase I project. A low-risk plan will be based on using existing, proven solutions to meet emerging requirements, while a high-risk plan will be based on applying solutions that are available today, but requires further proof for the embedded vision processor application. With both plans, power, latency, weight, and size of the processors and peripheral devices will be estimated. Risks and benefits associated with each approach will be clearly identified.; BENEFIT: Due to rapid improvements in camera technology, vision systems are now included in many defense applications, including those carried by the Soldier as well as fixed-position, unattended systems placed at key observation points. Development of a small, low power, image processor capable of faster processing of large video formats with sub-frame latency will be a critical enabler for many applications, including for example, unmanned air and ground vehicles, digital night vision, gun sights, wearable displays, and helmet mounted displays . The broad target market is embedded computation, with significant power savings gained by off-loading tasks from a general purpose processor to a dedicated multi-core image processor. The recent trend is to add embedded image processing to mobile systems, which dramatically increases required computation and leads to dramatic growth in power consumption. Commercial demand for a low-power, embedded image processor include a wide variety of end applications such as tablet, laptop, desktop and datacenter computers, mobile phones, video game consoles, high-speed communication devices, and graphics displays

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

2 SBIR/STTR records share this UEI (2013–2015). Reported award amounts total $299,999. Reported amounts are not federal obligations.

Phases: Phase I

Agencies: Department of Defense, National Science Foundation

Agency intelligence

Department of Defense

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