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Award details
- Awarding agency
- Department of Defense
- Branch
- Air Force
- Recipient company
- MICROELECTRONICS RESEARCH DEVELOPMENT CORPORATION
- Proposal award date
- 2014-06-20
- Contract end date
- 2015-03-02
- UEI
- M2WCCD39B593
- Solicitation number
- 2014.1
- Topic code
- AF141-096
Research abstract
ABSTRACT: Central Processing Units (CPUs) continue to grow in complexity while introducing higher speed clocks required to process data at extreme speeds. Advanced space grade, radiation-hardened processors are following this trend as processing requirements in space become more demanding, but for the full benefit to be derived from to faster CPUs support circuits must be developed that can match their speed requirements. A key component required to achieve high system throughput is a cache memory performance-matched to the CPU, including speed, radiation tolerance and power consumption. Discrete cache memories have been commercially available for many years built using various processes. Most products today are built in CMOS but do not deliver the speeds and radiation tolerance required of future space-grade systems. The goal of this project is to design and produce cache memory capable of supporting high performance space-grade CPUs with no wait-state memory accesses. Cache memory sizes must be sufficient to allow the CPU to operate at optimal speed while meeting all of the radiation, temperature and power supply parameters of the associated circuitry. Micro-RDC possesses design expertise, intellectual property and design tools capable of addressing these leading- edge goals with deliverables capable of supporting system requirements in the foreseeable future. BENEFIT: Delivery of cache memory performance-matched to high speed radiation hardened CPUs will support increased throughput of communications channels in satellite transponders as well as support other types of compute-intensive applications such as image processing and resource management. A high density 16 Mb monolithic SRAM L2 cache that can perform accesses at the MPU core frequency will significantly improve system processing performance.
Technology keywords
Not reported
Other awards by this recipient
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Awards with the same topic code
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Research funding history
45 SBIR/STTR records share this UEI (2006–2019). Reported award amounts total $31,438,573. Reported amounts are not federal obligations.
Phases: Phase I, Phase II
Agencies: Department of Defense, National Aeronautics and Space Administration
Agency intelligence
Department of Defense
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