SBIR/STTR Research Award

Radiation Hardened Cache Memory

Award identifier 76d8f5dd44268ab1b52e9ec5ec1445fb93b480f6ab6879d0d3598b70489c6386Awarding agency Department of Defense · Air Force

Award amount

$149,999

Program and phase

SBIR · Phase I

Award year

2014

Explore This Research Award in CaptureIQ

Research the technology, evaluate the recipient and agency, identify related opportunities, and explore potential follow-on work with CaptureIQ.

Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
MICROELECTRONICS RESEARCH DEVELOPMENT CORPORATION
Proposal award date
2014-06-20
Contract end date
2015-03-02
UEI
M2WCCD39B593
Solicitation number
2014.1
Topic code
AF141-096

Research abstract

ABSTRACT: Central Processing Units (CPUs) continue to grow in complexity while introducing higher speed clocks required to process data at extreme speeds. Advanced space grade, radiation-hardened processors are following this trend as processing requirements in space become more demanding, but for the full benefit to be derived from to faster CPUs support circuits must be developed that can match their speed requirements. A key component required to achieve high system throughput is a cache memory performance-matched to the CPU, including speed, radiation tolerance and power consumption. Discrete cache memories have been commercially available for many years built using various processes. Most products today are built in CMOS but do not deliver the speeds and radiation tolerance required of future space-grade systems. The goal of this project is to design and produce cache memory capable of supporting high performance space-grade CPUs with no wait-state memory accesses. Cache memory sizes must be sufficient to allow the CPU to operate at optimal speed while meeting all of the radiation, temperature and power supply parameters of the associated circuitry. Micro-RDC possesses design expertise, intellectual property and design tools capable of addressing these leading- edge goals with deliverables capable of supporting system requirements in the foreseeable future. BENEFIT: Delivery of cache memory performance-matched to high speed radiation hardened CPUs will support increased throughput of communications channels in satellite transponders as well as support other types of compute-intensive applications such as image processing and resource management. A high density 16 Mb monolithic SRAM L2 cache that can perform accesses at the MPU core frequency will significantly improve system processing performance.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

45 SBIR/STTR records share this UEI (2006–2019). Reported award amounts total $31,438,573. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration

Agency intelligence

Department of Defense

Back to SBIR/STTR Research Awards

Don't take our word for it. Ask AI about RFPCapture.

See what leading AI assistants have to say about RFPCapture and CaptureIQ.

Gemini opens without a prefilled question. The question is copied to your clipboard when the button works. You can also copy it here:

What is RFPCapture.com and its CaptureIQ platform from Smart Logic AI? How does it help federal contractors discover opportunities, evaluate bid/no-bid decisions, research government contracts, and prepare proposals? How does it compare with other federal capture platforms? Use independent sources where available.