SBIR/STTR Research Award

Next Generation Rad Hard Reduced Instruction Set Computer

Award identifier 2032b415d1a502ef11c0c194300ba5cf8d86965f54ca100a3a4564473aa8a8baAwarding agency Department of Defense · Air Force

Award amount

$149,611

Program and phase

SBIR · Phase I

Award year

2014

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
NHANCED SEMICONDUCTORS, INC.
Proposal award date
2014-06-20
Contract end date
2015-03-02
UEI
LATHGF1NRTC1
Solicitation number
2014.1
Topic code
AF141-097

Research abstract

ABSTRACT: Tezzaron proposes to create a microprocessor device based on an ARM M0 processor designed to be fabricated in the Honeywell S150 Rad-Hard SOI semiconductor process. The device will be designed for both stand alone and 3D circuit integration. In a 3D application the device can be die to wafer or wafer to wafer assembled providing a core set of SOC processor functions. BENEFIT: An ARM M0 processor device that is hardened has broad applicability to the Mil-Aerospace market. The performance of the M0 processor makes it a good candidate for real time flight control and the 3D integration feature can provided unparalleled performance at low power.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

21 SBIR/STTR records share this UEI (2008–2021). Reported award amounts total $9,451,098. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, Department of Energy, National Aeronautics and Space Administration

Agency intelligence

Department of Defense

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