SBIR/STTR Research Award

High Speed Digitizer for Remote Sensing

Award identifier 396dffdf7ba2484ec985df061d7652a4c2bd83634b1179592ace10b388ef4ba1Awarding agency National Aeronautics and Space Administration

Award amount

$124,637

Program and phase

SBIR · Phase I

Award year

2014

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
Alphacore, Inc.
Proposal award date
2014-06-20
Contract end date
2014-12-19
UEI
CXMPDDLFBCH3
Solicitation number
Not reported
Topic code
S1.02

Research abstract

Alphacore, Inc. proposes to design and characterize a 24Gsps (giga-samples per-second), 6-bit, low-power, and low-cost analog-to-digital converter (ADC) for use in a wide range of NASA's microwave sensor based remote sensing applications. The goal of this program is to provide an ultra-high-speed, low-power ADC that does both, provides excellent interfacing capabilities to top FPGAs and also has an optimized low-power spectrometer DSP backend available to be integrated on the same chip. The proposed ADC employs an innovative topology with high-bandwidth front-end sampling circuit combined with a flash-type ADC and encoder circuitry that simplifies FPGA interfacing. Innovative and effective digital calibration is used to guarantee spurious free Nyquist frequency band which is an important requirement in remote sensing applications.Comparable commercial ADCs are based on expensive and power-hungry bipolar transistor technologies such as indium phosphide (InP), gallium arsenide (GaAs) and silicon germanium (SiGe). Alphacore designs take advantage of the latest low-power, high-speed digital CMOS processes, resulting in ADC power consumption that is less than 1/8 of the power consumption of competitor ADCs. Using a CMOS process provides additional advantages in that we can leverage existing intellectual property (IP) to enhance the system-level integration of the ADC, e.g., on-chip digital calibration logic, data buffer memory, high-speed transceiver logic, and direct on-chip DSP capabilities.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

155 SBIR/STTR records share this UEI (2013–2026). Reported award amounts total $63,784,604. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Energy, Department of Commerce

Agency intelligence

National Aeronautics and Space Administration

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