Advanced Radiation Hardened Data Converter Architecture

Silicon Technologies Inc. (STI) proposes to develop a data conversion architecture using radiation hardened ADC and DAC converter technologies. The circuit topology will be based on a fully differential, redundant SAR ADC which utilizes three high speed comparators to enable single clock conversion at 25MHz with 14 bit data conversion. The circuit design will be based on previous research sponsored by DARPA and the Air Force which has resulted in the development of a revolutionary new design tool called ADONIS. ADONIS uses a structured Radiation Hardened by Design technique that greatly simplifies the design, layout, and verification of a circuit. The ADONIS tools contains a Rad Hard by Design Analog Cell Library (RADL) which provides the basic components required for the design of the SAR This structured design approach has the advantage of 1) Consistent cell structures with Rad-hard design, 2) Repeatable structures which controls leakage, 3) Interactions between cells are known at design time, 4) Faster design cycle resulting in a savings of more than 2x standard design time, 5) Portability between different CMOS processes, 6) Noise and IR reduction due to a proprietary power and ground mesh, and 7) Standardized Radiation Hardened by Design transistors and other functions.