Real Time Adaptable ROIC for improved Power and Performance Optimization in Imager Systems

There are two objectives of this effort: 1) demonstrate an adaptable, scalable and dynamically configurable digital ReadOut-Integrated-Circuit (ROIC) architecture and 2) establish the foundation for the successful transitioning of this technology to product. This new technology is important because the performance of the ROIC can now be optimized for several different applications in contrast to present technologies where optimal ROIC performance is application specific. With this technology, optimized performance of a ROIC, includes the ability to adapt to different pixel pitches, scale to different detector sizes (rows and columns of pixels) and dynamically make power and performance trade-offs based on an applications requirements. The adaptable and scalable capability of this ROIC technology is based on the concept of a data slice (DS) while the dynamic configuration capability is based on the ability trade-off the performance and power of an SDM analog-to-digital convertor (ADC). The circuit design of the DS is modular and is built from a library of components that are rearranged but not redesigned. This design methodology enables lower cost custom digital ROICs with shorter design cycles compared to a traditional approach.