Side Channel Attack Testbench Emulator (SCATE)

Side channel analysis and fault injection are a solid part of the relevant attack space for any chip that can be physically reached by an attacker. Both allow key extraction from cryptographic implementations, and fault injection specifically allows complete takeover of devices. Current commercial chip design tools do not offer integrated analysis to verify resistance against these attacks at design time. The effect is that countermeasure design is a manual and error-prone process: multiple tape outs may be required, and even for experts it is nontrivial to pinpoint and mitigate sources of vulnerability. The tools being created allow an EDA designer without specific side channel and fault injection knowledge to create a design with countermeasures, without the need to perform post silicon analysis and a silicon re-spin. This is achieved by automatically detecting points of vulnerability, and either suggesting or automatically implementing design changes to mitigate these. With back-end physical design tool costs and wafer mask cost becoming staggeringly high for advanced silicon process nodes, these tools can result in shortened development schedules and significant cost savings.