SBIR/STTR Research Award

Incorporation of trust into integrated circuit (IC) and field programmable gate array (FPGA) design

Award identifier 4949f518b8a32b6033f0baea64131fbed9779f305ba5d12d867a7919f1f713f3Awarding agency Department of Defense · Army

Award amount

$99,962

Program and phase

SBIR · Phase I

Award year

2011

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Award details

Awarding agency
Department of Defense
Branch
Army
Recipient company
EDAPTIVE COMPUTING INC
Proposal award date
2011-02-14
Contract end date
Not reported
UEI
ULSZZUD8P7W7
Solicitation number
2010.2
Topic code
OSD10-A07

Research abstract

As designs continue to progress in complexity, integration of third party assets has become a standard practice in hardware designs. Third party design integration, while reducing the complexity of the design process, always introduces risk in terms of the access to the internal components. These introduced elements are sometimes enclosed in a black-box, where system integrators cannot peek. Through the application of the VT-IP solution, we provide a framework for allowing more visibility and control over the functionality of integrated designs into FPGA hardware. The solution also provides a methodology for protecting critical device elements from adverse behavior in a third party design. The resulting capabilities will result in a marked increase in trust for FPGA integrators.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

92 SBIR/STTR records share this UEI (1999–2023). Reported award amounts total $45,452,067. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, National Science Foundation

Agency intelligence

Department of Defense

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