SBIR/STTR Research Award

Field Programmable Gate Array (FPGA) Physical Unclonable Functions

Award identifier 9cc7f9e7e5d218b0b546bef43656e99556766539ad49470b5cb052c2623999caAwarding agency Department of Defense · Army

Award amount

$100,000

Program and phase

SBIR · Phase I

Award year

2011

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Award details

Awarding agency
Department of Defense
Branch
Army
Recipient company
GRAMMATECH INC
Proposal award date
2011-02-07
Contract end date
Not reported
UEI
CBXRSPNRF8F9
Solicitation number
2010.2
Topic code
OSD10-A02

Research abstract

Physically Unclonable Devices (PUFs) have many applications in security and digital rights management. These devices are used in creation of random number generators used to seed key generation and one-time pad construction for encryption applications. They are also used as a means of uniquely authenticating a piece of hardware or computing device. Given the large applicability of field programmable gate arrays (FPGAs), it is desirable to have PUFs that can be applied to these commercial devices. However, existing FPGA-based PUFs have relatively low entropy and security. We propose a new design process that will produce new PUF architectures with higher entropy and security.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

132 SBIR/STTR records share this UEI (1989–2025). Reported award amounts total $51,342,070. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Homeland Security, National Science Foundation, Department of Commerce

Agency intelligence

Department of Defense

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