SBIR/STTR Research Award
Innovative Approaches to Low Power, Sub-Threshold Electronic Circuits
Award amount
$744,039Program and phase
SBIR · Phase IIAward year
2010Award details
- Awarding agency
- Department of Defense
- Branch
- Defense Advanced Research Projects Agency
- Recipient company
- ADESTO TECHNOLOGIES
- Proposal award date
- 2010-06-04
- Contract end date
- 2012-06-03
- UEI
- Not reported
- Solicitation number
- 2008.2
- Topic code
- SB082-045
Research abstract
The primary goal of a Phase II funded program will be to implement, fabricate, and characterize in standard CMOS an embedded memory block that can be used in an ultra low energy system either as a stand-alone non volatile memory or as an enabling block. As such, the Phase II proposal is intended to fund a project within Adesto to support implementation of the circuit blocks and techniques developed and proposed in our Phase I program on an actual silicon testchip.
Technology keywords
Not reported
Awards with the same topic code
Verified by an exact topic code match. This is not a text-similarity match.
- Innovative Approaches to Low Power, Sub-Threshold Electronic Circuits
- Innovative Approaches to Low Power, Sub-Threshold Electronic Circuits
- Innovative Approaches to Low Power, Sub-Threshold Electronic Circuits
- Innovative Approaches to Low Power, Sub-Threshold Electronic Circuits