Innovative Approaches to Low Power, Sub-Threshold Electronic Circuits

This program proposes to demonstrate an ultra-low power design methodology and circuits for digital logic employing advanced dynamic voltage scaling (DVS) for asynchronous NULL Convention Logic (NCL) circuits operating in sub-threshold to super-threshold voltage regimes. The power supply voltages of logic block partitions will be independently set by on-chip voltage controllers based on the data processing rate requirements for each block. The proposed development includes design of sub-threshold to super-threshold level converter circuits, DVS control block, DC-DC converter, and supporting design infrastructure to implement digital logic System on Chip (SoC) designs targeted at infrared (IR) camera electronics.