SBIR/STTR Research Award

Ultra Low Power Electronics for Autonomous Micro-Sensor Applications

Award identifier 9c41efa1c2cc69a71dc3ecee4c490d56d613a9c0ed415d0de830fda13ba762f3Awarding agency Department of Defense · Air Force

Award amount

$99,606

Program and phase

SBIR · Phase I

Award year

2010

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
CAMGIAN CORPORATION
Proposal award date
2010-01-14
Contract end date
2010-10-14
UEI
HVLBJJBVSUP7
Solicitation number
2009.3
Topic code
AF093-159

Research abstract

This program aims to develop an ultra low power System-on-a-Chip (SoC) technology that will enable >10x improvements in size and endurance over current generation wireless micro-sensor networks. This will be achieved through the integration of advanced circuit and architectural design methods targeted to improve wireless micro-sensor node performance in four critical performance parameters: (1) digital circuit design methodologies that enable the energy consumption of the chip to be dynamically matched to the performance needs of the system;(2) digital circuit design styles that minimize crosstalk noise to radio-frequency (RF) and other analog circuits;(3) advanced power and voltage gating and scaling techniques that reduce idle (leakage) energy consumption; and (4) System on Chip (SoC) design architectures optimizing energy, cost, and size. These elements will be integrated with a unique RF circuit architecture which has improvements in RF switches for signal steering to antennas, power amplifiers for transmitter output, direct digital synthesis, and high-frequency mixers for carrier modulation and received signal down-conversion. While the technical approaches to intelligent, adaptive, ultra-low power, low-noise circuits will be generic and broadly applicable to DoD systems a specific hardware architecture will be developed based on an intelligent wireless micro-sensor node. BENEFIT: The successful program will lead to improvements in the cost, size, weight, and power (CSWAP) metric of wireless sensors. The CSWAP reduction is achieved partially through dramatic reduction of the electronics power and energy consumption which leads directly to smaller power source requirements and higher integration capability. A further driver of CSWAP reduction is the use of NCL clockless logic which gives lower noise crosstalk from the digital processing circuitry to the critical RF and analog circuits. An additional benefit of the program which drives CSWAP improvement is the integration of NCL digital processing circuits with an innovative new RF circuit architecture which has improvements in critical performance areas. The initial products targeted for deployment will be wireless micro-sensor systems such as are used for border security, military intelligence, military battlefield surveillance, and SmartGrid power system monitoring.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

8 SBIR/STTR records share this UEI (2009–2024). Reported award amounts total $1,474,439. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense

Agency intelligence

Department of Defense

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