SBIR/STTR Research Award

Readout Integrated Circuit (IC) Technology for Strained Layer Superlattice Photodetectors

Award identifier f3a64e601aa531a6022ffe891e40e2f034e5efa2bb48491b379ccbf127a4ea09Awarding agency Department of Defense · Air Force

Award amount

$100,000

Program and phase

SBIR · Phase I

Award year

2010

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
Intrinsix Corp.
Proposal award date
2009-12-16
Contract end date
2010-09-16
UEI
E6DUNB8BVW64
Solicitation number
2009.3
Topic code
AF093-160

Research abstract

Intrinsix proposes a modular Read Out Integrated Circuit (ROIC) based on a uniquely architected overlapping serpentine read path that enables the use of high dynamic range sigma-delta modulator based analog-to-digital converters (ADC) for imaging applications. We have coined the project as “SnakeEye”. The primary objective of this effort is to provide the specifications and architectural details for the design of a low cost ROIC optimized for use with Strained Layer Superlattice Photo-detectors for Un-Manned Air Vehicle(UAV) applications that increases the dynamic range of the ROIC 4 to 16 times, and enables rapid deployment of new sensor technology for UAV applications. SnakeEye’s benefits are accomplished by leveraging several innovations: programmable SDM data converter design, overlapping serpentine ROIC read pattern, and fault-tolerant configuration of SDM-ADCs. BENEFIT: The three key benefits are: 1) High dynamic range enabled by Sigma-Delta Modulator (SDM) based serpentine read channel a. Fault & single event tolerance using redundant ADCs b. High SNR and reduced fixed pattern noise by digitally combined and compensated ADCs 2) Rapid lower cost deployment of new sensors while improving on SWaP of high end instruments. a. Utilizes industry standard, low power high-speed serial interfaces to simplify interchange of instruments b. Customized analog interface coupled to common signal acquisition block enables rapid deployment of new sensors, regardless of configuration or manufacturer 3) Performance of modern (sub 100nm CMOS) technology a. Column pitch down to 5um b. High throughput using multiple ADCs c. Enables integration of signal processing and information compression

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

11 SBIR/STTR records share this UEI (2010–2021). Reported award amounts total $9,937,748. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense

Agency intelligence

Department of Defense

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