Minimally-Invasive Radiation Hardened Semiconductors

We have developed engineered epitaxial layers based on nanostructure technology that can be applied in hardening advanced deep submicron commercial silicon devices (90nm and smaller line width) against total dose degradation, single event upsets (SEU) and single event transients (SETs) by minimizing collected photocurrents (electron-hole pairs) via recombination centers.   This could provide an ideal solution for deep submicron commercial architectures.  Texas Instruments (TI) has reviewed our nanostructure-engineered epitaxial layers and is interested in developing the technology for use in their expanding radiation hardness assured (RHA) military and aerospace product line.  Success of this project in a TI fab would open up possibilities for running this material in other domestic deep submicron fabs. Radiation Assured Devices in conjunction with Ball Aerospace is currently running a test lot of engineered substrates with TI.  Under this proposed Phase I effort we would characterize the test chips obtained from the current TI run (due for delivery in January 2009) for radiation hardness, electrical performance (power, speed leakage, etc) and long term reliability and prepare a Phase I final report in conjunction with TI on migrating the engineered substrate technique to 90nm or smaller technology nodes.    BENEFIT: The nanostructure-engineered substrates we are proposing would be an ideal solution to leverage commercial integrated circuit architectures and provide radiation hardened capability without any required changes in the IC design or the fabrication process.  The only change would be that a special nanostructure-engineered substrate would be substituted for the standard raw substrate that would typically be used.  In this manner, a radiation hard version of these Integrated Circuits could be produced without any changes required in the IC design or to the wafer fabrication process.