90nm Low-Power Radiation-Hardened Metal-Programmable System-on-a-Chip

Silicon Space Technology (SST) working with Texas Instruments (TI) proposes to demonstrate a 90nm low-power radiation-hardened (RH) metal-programmable system-on-a-chip (SOC) cell library. This will be accomplished by defining, designing, simulating and laying out a demonstration circuit that could eventually be turned into a commercial product. A base slice will be developed upon which the demonstration circuit can be fabricated. The elements of the cell library will be designed using the Texas Instruments’ C027 90nm commercial process augmented by Silicon Space Technology’s Harden-By-Isolation (HBI) techniques. Many customers would find SST’s 90nm low-power radiation-hardened (RH) metal¬-programmable SOC cell library design approach very appealing as compared to custom ASIC or FPGA alternatives due to improved costs and/or performance. Because the silicon is fabricated by Texas Instruments, one of the largest semiconductor companies in the world, there would be additional benefits associated with a reliable supplier providing state-of-the-art defect density and circuit yields. Due to the $750K Phase II limit and the high cost of 90nm processing, it will not be possible to produce prototypes – therefore only the design of the demonstration circuit will be completed. BENEFIT: Benefits: Space system designers who need high performance application specific integrated circuits (ASIC’s) currently have two choices: full custom design using a Harden-By-Design (HBD) standard cell library or a hardened FPGA. A space-qualified 90nm low-power radiation-hardened (RH) metal-programmable system-on-a-chip (SOC) cell library would give designers a third option that would outperform the other two in many ways. Improvements over HBD standard cell library The problem with any standard cell library design is the high NRE associated with the design effort. This design method requires a full set of masks to fabricate the circuit. At the 90nm technology node, this can cost almost $1 Million. The silicon wafers for this type of design must start at the beginning of the manufacturing process, adding weeks to the fabrication schedule. A metal programmable cell library design requires only one third of the masks to be generated, thus saving much of this cost. The silicon is pre-fabricated through two thirds of the process, so the cycle time to obtain functioning circuits is much lower. To ensure radiation hardness a HBD cell library must be used. When using these cell libraries there is a typical penalty of 2X the power, speed, and area over commercial cell libraries. Because SST’s low-power radiation-hardened (RH) metal-programmable SOC cell library uses our proprietary HBI hardening techniques, designers are able to obtain the same performance as with commercial cell libraries. The design risk is also reduced because, with the metal programmable approach, the underlying designs are pre-verified. The base layers can be used with multiple designs, reducing inventory costs and production lead times. There would be lower design complexity with this approach. The customer has only to work with routing of the base fabric. There is no requirement for understanding the lower levels. The design of the unit cell, or fabric, in the base layers will be designed specifically to the requirements of low power and for frequent use of spatially redundant storage cells. Improvements over FPGA’s FPGA’s can be a very attractive solution for designers due to the capability to reprogram the circuit if needed. However there are several serious issues with FPGA’s. FPGA’s typically use five times the power of standard ASICs. Speed is also an issue with FPGA’s. The metal programmable approach would have the power, speed, and capacity similar to Standard Cell ASICs, consuming 1/5 the power of an FPGA and more capacity. There would be substantial benefits to the customer by large reductions in power over FPGA designs. The lower power requirements would provide additional benefits at the system level for power supply design and thermal management. According to an FPGA Project Survey by FPGS and Programmable Logic Journal, the most painful and difficult problem for FPGA design teams is getting timing closure on their design. The timing closure process generally involves multiple iterations of RTL modification, constraint specification, synthesis, and place-and-route. On large devices, one pass through this cycle can take more than 24 hours, and some teams are experiencing as many as 50-60 iterations before their design converges. The metal programmable design would provide timing closure similar to Standard Cell ASICs. SST’s proposed low-power radiation-hardened (RH) metal-programmable SOC cell library would also provide a much higher level of radiation tolerance than is available for FPGA’s. FPGA’s for the space community use HBD techniques with the penalties described above. These penalties in speed, power and size are avoided by SST’s HBI technology. Summary of Opportunity With the advantages outlined above many customers would find SST’s 90nm low-power radiation-hardened (RH) metal-programmable SOC cell library design approach very appealing. Because the silicon is fabricated by Texas Instruments, one of the largest semiconductor companies in the world, there would be additional benefits associated with a reliable supplier providing state-of-the-art defect density and circuit yields.