Space Qualified, Radiation Hardened SDRAM Memory

Space Micro has developed RHBD innovation hardening techniques, HF-Core Memory Controller and “Architecture” Hardening, that in combination with other known industry standard hardening techniques, plus the innovative use of embedded DRAM and ASIC technologies. We propose to apply these techniques to design and manufacture a radiation hardened, dense and high-speed RH-eDRAM memory integrated circuit from commercial technologies. The new design techniques are portable across advanced geometry, CMOS foundries and can be easily re-applied as commercial SDRAM suppliers migrate to smaller geometries and increased memory sizes. In Phase I, Space Micro demonstrated the new RHBD radiation mitigation techniques, converted the techniques to circuits and radiation test the innovation. Using these results, we will provide a refined design of the RH-eDRAM design to be manufactured in Phase II. The resulting design will meet and exceed Air Force and other satellite radiation and reliability design goals, providing future satellite hardware designers a dense DRAM memory integrated circuit for computing platforms and solid-state mass memories. BENEFIT: Space Micro’s HF-Core Memory Controller and resulting RH-eDRAM integrated circuit will provide the Air Force, NASA and commercial satellite communities a continuing supply of radiation hardened DRAM memories. Specifically, the benefits and expected performance of RH-eDRAM are: • Use of commercial ASIC processes to manufacture radiation hardened DRAM • Use of known radiation ASIC process performance >100 krad and no SEL • SEU and SEFI hardening by “architecture” using the HF-Core Memory Controller eliminate the need for a full RHBD library, providing: o DRAM memory controllers at full commercial speeds (125 to 250 MHz) o SEFIs in memory controllers detected and mitigated without performance loss o Expected SEU/SEFI probability of 1E-7 errors/day (in GEO) in the HR-Core Memory Controller o Hamming Code EDAC detection & correction of eDRAM SEUs • Demonstration RH-eDRAM memory results in 512 Mbit of available memory, performance: o >133 MHz speed o >100 krad (Si) total dose o No SEL >70 MeV/mg/cm2 o SEU corrected memory, SEU rate of 1E-4 unrecoverable errors per device-day o No SEFI or multiple bit upsets at a rate of 1E-6 hangs or double bit errors per device-day • RH-eDRAM control logic and memory can run at full commercial speeds and low power