Space Qualified SDRAM Memory

The Phase 1 effort is aimed at finding the specific physical defects which prevent a Commercial SDRAM at the 512 Megabit density from being Space Qualified. The goal is to find the exact failure locations of Radiation “Soft” circuits. Scanning Laser Microscopy will locate latch-up sites. Heavy Ion Exposure will be used to find multiple bit error rates. Emission Microscopy will be used to locate leakages induced by Total Ionizing Dose exposure. During Phase 2, the design team of the Commercial SDRAM manufacturer has agreed to partner with Micro-RDC to modify the SDRAM circuits so that higher radiation levels can be tolerated. The goal is to make the Space Qualified SDRAM immune to latch-up, tolerate greater than 100 krad(Si) total ionizing dose, and work over the Mil-Spec temperature range. The SDRAM will also remain functional due to Single Event Effects, but Single Event Upsets of data bits is anticipated to be corrected at the system level using Error Detection and Correction methods. A survey of end customers of Space Qualified SDRAMs will also be conducted during Phase 1 so that the required form and function can be determined.