Space Qualified SDRAM Memory

Silicon Space Technology (SST), working with Texas Instruments (TI), proposes to demonstrate an innovative approach for manufacturing radiation hardened (RH) high-density SDRAM¡¯s for space applications by adding two proprietary RH modules plus a simple stacked capacitor structure to TI¡¯s baseline 130nm process flow. SST has solved the major space radiation problems, Single-Event Effects (SEE), Total Ionizing Dose (TID) & Dose Rate (DR), by combining process modifications and layout design innovation. Our proven-in-silicon approach enables production of radiation-hardened integrated circuits at leading-edge circuit densities within any commercial silicon foundry, for use in both terrestrial and space systems. Sequences of radiation tests have shown SST¡¯s Buried Guard Ring (BGR) significantly improves SEE performance (e.g., SEL, SET, & SEU). BGR also significantly improves Dose Rate performance by >23x higher than non-BGR protected circuits. SST¡¯s Parasitic Isolation Device (PID) structures have shown complete TID immunity to > 1Mrad. These methods do not adversely affect either circuit performance or yield. The simple stacked capacitor will be based on structures previously used by mainstream DRAM manufacturers. While this will not result in state of the art DRAM densities, it will enable manufacture of much denser RH memories than currently available.