Rad-Hard-Strategic, 14-bit, 150 MSPS ADC

We will develop a rad-hard-strategic, 14-bit, 150 MSPS, ADC. Major challenge is maintaining part speed, while hardening it to radiation. The traditional approach to photo-compensation involves adding a “compensating” transistor per “circuit” transistor. This method results in doubling the capacitance and introduces coupling from the substrate at every junction, greatly impairing part’s sampling rate. Bill Poland’s (Nu-Trek) innovation is to increase bias during radiation. The increased bias raises the level of radiation/photocurrent that will upset circuit operation. This approach has already been used in Nu-Trek’s monolithic Nuclear Event Detector, enabling the precise measurement of minute transistor photocurrents. Other innovations include: (1) A Master Slave Sample and Holds between stages versus single Sample and Hold; (2) Interstage nulling in the current domain, not the voltage domain, minimizing voltage slew rate against parasitic capacitances; (3) Bootstrap self calibration of the three DACs in the three front stages; and (4) Differential inputs that operate between +2.5 volts and -2.5 volts to accommodate a broader range of applications, including video. ADC is based on a rad-hard 12-bit ADC that Wayne Dietrich (Raytheon) designed for the Navy.