Ultra-Fast Level 2 Cache SRAM for High-Performance Military and Spaceborne Computing

In this proposal we discuss the development of an ultra high-speed synchronous SRAM suitable for use as an embedded level 1 or external level-2 cache memory. The state-of-the-art radiation tolerant/hardened memory devices are of an asynchronous design with access times of 17 to 30ns. The synchronous memory we are proposing has a targeted access time of <3ns (nearly a factor of 6 improvement over the current fastest military devices) and an 18Mbit density (configured for level-2 cache data bus for high-speed processing). This type of memory is extremely popular in the commercial marketplace, but does not exist at all today in a military/rad-hard version. The device we are proposing would be targeted to a commercial fabrication process would use a novel reverse body bias HBD technique to achieve exception total dose hardness without sacrificing speed. Because our proposed SRAM cell is very close in size to a commercial SRAM we could achieve a cost/bit that is potentially a factor of 10 lower than current military asynchronous SRAMs.