Next Generation Programmable Gate Array

Existing Field Programmable Gate Arrays (FPGAs) provide space-based users with an awkward choice between high performance commercial devices that are not capable of functioning reliably in a space-borne environment, or low performance devices that are specially hardened for space environments. This unacceptable compromise forces space-based applications needing high performance to incur higher NRE costs to develop hardened, mission-specific cell-based ASICs that typically do not provide the flexibility needed for future enhancements. What is needed is a high performance, flexible, field-programmable platform that is capable of operating reliably in harsh environments. This program focuses on the (continued) development of a general-purpose, field-programmable signal processing platform. The goal(s) of the platform ASIC include: 1. Computational efficiencies for signal processing algorithms measured in BOPS/Joules within a factor of two of a standard-cell based ASIC performing an equivalent set of operations. 2. Programmable in a hardware description language at a coarse level. 3. Capable of changing algorithm sets in one clock cycle. 4. Capable of being implemented in multiple processes, including rad-hard SOI 5. Capable of going from code verification to deployment in two weeks or less.