SBIR/STTR Research Award

Dual Chip Approach to Radiation Hardened Logic

Award identifier dbd07fd5f4387d88820917837fee81d5e0fcceff08e2127316a8cccdfef4bf94Awarding agency Department of Defense · Air Force

Award amount

$99,977

Program and phase

SBIR · Phase I

Award year

2006

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
MICROELECTRONICS RESEARCH DEVELOPMENT CORPORATION
Proposal award date
2006-04-12
Contract end date
2007-05-12
UEI
M2WCCD39B593
Solicitation number
2006.1
Topic code
AF06-256

Research abstract

We wish to offer users nearly ASIC density (20X higher logic density than FPGAs), yet allow them to develop their systems with off-the-shelf FPGA-based parts. The core idea is to use a new high-density non-rad-hard FPGA for development, and an electrically and timing equivalent, rad-hard by design (RHBD) Structured ASIC in the same package for flight. This is much like using commercial Actel FPGAs for development, and their rad-hard versions for flight. Users would develop their systems with our FPGAs, and later replace them with factory-programmed rad-hard structured ASICs for flight, with close to zero risk of conversion problems.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

45 SBIR/STTR records share this UEI (2006–2019). Reported award amounts total $31,438,573. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration

Agency intelligence

Department of Defense

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