Rad-Hard Very High Data Rate Forward Error Correction Codec

Space Micro, Inc. proposes to develop a radiation-hardened forward error correction (FEC) codec ASIC for use in very high data rate, space-based, laser communication systems. Our proposed codec uses an innovative combination of a Reed-Solomon code concatenated with other short binary block codes, and a variable-depth interleaver. The code achieves outstanding error correction performance: 10 dB or more of net coding gain for random errors (at BER = 1E-12), and extremely long burst error correction - the duration of correctable burst errors is effectively limited only by the size of the codec's interleaver memory. During SBIR Phase I we developed a Monte Carlo software simulation of a realistic space LaserCom channel and demonstrated the BER performance of our FEC code; and we implemented a prototype FEC codec on an FPGA development board. During SBIR Phase II, we will develop a rad-tolerant single-chip ASIC version of our FEC Codec which operates up to 2.5 Gbps. We also will perform extensive testing and conduct demonstrations of this proof-of-concept prototype FEC Codec ASIC. Space Micro's extensive experience in both FEC coding and radiation hardening of microelectronics makes us particularly well-qualified to address this SBIR topic.