High Data Rate Error Correction

In this SBIR, Efficient Channel Coding (ECC) will develop an innovative Forward Error Correction (FEC) architectures that are optimally suited for burst error correction and feasible for 40 Gbps data throughput applications. Design goals include improving BER performance, minimizing decoding latency, and lowering codec complexity / power consumption for on-satellite processing. Today's 40-Gbps FEC solutions are mostly RS code based, contrasting to ECC's product code technology that uses innovative iterative (turbo) decoding to obtain higher coding gains, while keeping the complexity practical for Application Specific Integrated Circuit (ASIC) implementation. Among such codes, RS product (RSP) codes are extremely suitable due to their inherited burst error control capability, significantly improved BER performance, and complexity advantages Some other iterative FECs will also be investigated with Hard Input Hard Output (HIHO), or simplified Soft Input Soft Output (SISO) decoding algorithms. A range of suitable codec will be selected in Phase I and the Field Programmable Gate Array (FPGA) implementation of a selected codec(s) will be developed and tested in Phase II. Eventually, a radiation hardened ASIC device will be developed in Phase III to operate at 40 Gbps.