High Data Rate Error Correction

Space Micro, Inc. proposes to develop a radiation hardened forward error correction (FEC) codec ASIC for use in very high data rate, space-based, laser communication systems. Our proposed codec uses an innovative combination of a Reed-Solomon code concatenated with other short binary block codes, and a variable-depth interleaver. The code achieves outstanding error correction performance: 10 dB or more of net coding gain for random errors (at BER = 1E-12), and extremely long burst error correction - the duration of correctable burst errors is effectively limited only by the size of the codec's interleaver memory. Our innovative codec hardware design has a relatively low computational complexity that is feasible for implementation in FPGA and ASIC technology at data rates up to 40 Gbps and above. Radiation hardening is provided through a comprehensive "hard by design" approach, including the use of an innovative, inherently rad-hard decoder architecture and other logic design techniques, as well as a rad-hard ASIC process. Space Micro's extensive experience in both FEC coding and radiation hardening of microelectronics makes us particularly well qualified to perform this R&D, and insert the resulting IC product into DoD and NASA programs.