Receiver on Chip Signal Techniques and Reconfigurable Simulations (ROCSTARS)

The latest generation of the USAF's Monobit receiver is being designed as a receiver on a chip (ROC). The ROC will consist of an analog to digital converter (ADC) and a Fast Fourier Transform (FFT) unit on one silicon substrate and simulations have shown its ability to process pulsed RF signals. Systran Federal Corp. (SFC), along with Dr. Chien-In Henry Chen of Wright State University (WSU) and his associates and former associates and Northrop-Grumman Corporation (NGC), proposes a plan to simulate how the architecture will handle various signal modulation schemes. SFC's Phase I effort will consist of three areas. First we will put together a team consisting of the engineers responsible for the original and latest Monobit receiver architectures and the end user of the ROC. Second, we will use the team's input to research detection schemes that are currently being used in electronic warfare (EW) receivers and other schemes that look promising. We will then select a representative scheme or set of schemes to demonstrate. The final area will be the simulation of the chosen detection algorithm first in a simulation environment such as MATLAB and later in VHDL code aimed at the Virtex 4 platform as time allows.