Hardware in the Loop Operational Testing for Analog VLSI Image Processor Design

The objective of this project is to perform Hardware-in-the-Loop (HWIL) operational testing and analysis in support of critical BMDO missions using spatio-temporal image filtering hardware previously developed by Computational Sensors Corporation (CSC). This hardware supports, and is enabling to, BMDO program algorithms that flow down to major missile defense systems. This testing will use simulated and real-world government supplied imagery addressing critical boost phase and mid-course issues of RV detection and micro-dynamics based identification, closely spaced object discrimination in cluttered background environments, and high frequency spatial and temporal filtering for hardware compression. The simulation and hardware development work to date is ready for extensive HWIL testing validation to guide further application-optimized technology development. Specifically, these results will determine the key parameters and architectural features to drive a new analog VLSI chip design tailored optimally for supporting these tasks and suitable for captive flight-testing. This design will be more compact and consume less power than digital alternatives. In Phase I we will produce a chip architecture derived from HWIL results supported by extensive simulations performed to validate the new chip architecture filtering capabilities. Commercial, integrated, analog image processors are ideally suited for compact, low power, military imaging applications. Analog image processing technology may also be applicable in many other commercial areas including automatic inspection, biometric identification, and other machine vision applications.