Voltage Translation FPGA using Opensource Flows for countering Obsolescence

Alphacore is proposing a voltage translation FPGA chip and associated EDA toolchain to program the device. We strive to achieve the DMEA mission of “Deliver microelectronics solutions to meet Department of Defense needs” with this plan of work. Field-programmable gate arrays are a class of microelectronics which can be programmed per use for a specific task, which is different than an application specific chip (ASIC). While we upgrade microsystems from older technologies to newer technologies and packages, it’s very advantageous to have an FPGA in the right package format that can do optimal voltage translation by using programmable LDOs and I/O logic. The FPGA will route between the high voltage and low voltage domains as required by the DOD integrator, where programmability will allow maximal reuse while shifting up or down between the voltage domains while routing between the two on a programmable CLB and routing matrix. For advanced scenarios like automated packet routing of the data we can also use the logic.  The defense electronics obsolescence market is projected to grow from 2.5 to 3+ billion dollars in 2025 and we wish to solve the problems of integrating older systems working on 3.3, 5V or above supplies with more state-of-the-art systems at 2V and below. We do so by adhering to the following:Use US source chips in trusted foundries (Globalfoundries and(or) Skywater)Propose a toolchain and an adaptable FPGA architectureApply state of the art automation in design of the FPGA and its important components (I/O LDO, FPGA CLBs)Incorporate root-of-trust IP to ensure security and reliabilityWorking on a plan of chip tapeout, board design, testing and characterization so that we can satisfy and outperform DMEA and DOD needs in systems requiring programmabilityPlan for packaging in a plastic leaded package form-factor Bringing in research (ASU) and commercial (Quicklogic) partners together to achieve a high quality prototypeOpenFPGA is an open-source framework designed to automate and accelerate the development of customizable FPGA architectures. It addresses the long development cycles and high human effort required for FPGA development. The production flow takes an XML-based FPGA architecture description as input and generates gate-level Verilog netlists of the whole FPGA fabric that can be fed into a physical design backend flow to obtain a complete layout. This flow can autogenerate testbenches to perform functional verification. Synopsys design constraint (SDC) files are also autogenerated to enable timing-driven backend flows and to conduct timing analysis. The end-user flow allows FPGA users to map applications written in Verilog onto the FPGA developed using the production flow. A Verilog design or application is provided as an input to this flow. The product is a bitstream for configuring the FPGA fabric. This flow provides functionality like standard vendor tools, e.g., AMD/Xilinx Vivado or Intel/Altera Quartus.