SBIR/STTR Research Award

Low Cost Technologies for Manufacturing of Thin Film Lithium Niobate

Award identifier 1024271b9ca7b200356fda68cd4a8536948c1e8ecaf48388dced1db1ca059029Awarding agency Department of Defense · Air Force

Award amount

$199,872

Program and phase

STTR · Phase I

Award year

2025

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
PHASE SENSITIVE INNOVATIONS INC
Proposal award date
2025-07-11
Contract end date
2026-01-11
UEI
LJMKLES23319
Solicitation number
25.A
Topic code
AF25A-T001

Research abstract

Since thin-film lithium niobate (TFLN) wafers became commercially available, they have quicklyemerged as one of the most promising platforms for photonic integrated circuits (PICs) due to theirbroadband transparency, large Pockel's coefficient, and significantly improved integration compared tobulk LN technology. Despite rapid technical advancements worldwide, there is only one Asian waferprovider for high quality TFLN wafers, who has perfected the crystal ion slicing process for TFLN wafermanufacturing. This is partly due to the lack of a dedicated, cost-effective ion implantation serviceprovider in the U.S. that can generate the high-dose defect layers required for crystal ion slicing. Toaddress this limitation, we propose two alternative TFLN manufacturing approaches that do not rely onion implantation. We will collaborate with Penn State University to develop a low-cost TFLN wafermanufacturing process based on mechanical thinning and polishing, where uniform polishing is ensuredby introducing metal polishing stops through a highly selective etching process and a lift-off metaldeposition process. Additionally, we will work with SRI International to develop a controlled spallingprocess that allows for the controlled cracking of a thin LN film along a crystal facet parallel to the wafersurface, with film thickness determined by a metal stress layer applied to the top surface. In Phase I, wewill focus on developing a defect-free wafer bonding process with engineered stress levels to meetsubsequent processing requirements. Two CMP processes will be developed: the first to thin an LN waferto less than 5µm with nonuniformity below 1µm, and the second to polish the LN film down to 600nmwhile reducing nonuniformity to less than 30nm. The high-selectivity wet LN etch process will be refinedto maximize selectivity between the LN and SiO2 stop layer. Parallelly, we will optimize the controlledspalling process to enhance film uniformity and size. Proof-of-concept experiments will be conducted tovalidate the manufacturability and scalability of the spalling process. Finally, we will evaluate bothapproaches based on their benefits, risks, and costs, which will guide our Phase II work plan. With ourextensive experience in TFLN PIC development and manufacturing, and the introduction of these newcost-effective manufacturing approaches, PSI is well-positioned to establish a fully integrated U.S.-basedTFLN PIC foundry capable of producing a diverse range of TFLN PIC products using in-house TFLNwafers.

Technology keywords

Not reported

Other awards by this recipient

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Awards with the same topic code

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Research funding history

69 SBIR/STTR records share this UEI (2010–2025). Reported award amounts total $32,859,234. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Commerce, Department of Energy

Agency intelligence

Department of Defense

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